A conventional NAND EEPROM (Electrically erasable programmable read only memory) array block is formed by a series of floating gate transistors coupled in series between a select drain transistor and a select source transistor. The select drain transistor is coupled to a data transfer line called bit line (BL) and the select source transistor is coupled to a source line. Each floating gate transistor is a memory cell having a floating gate which is programmed and erased using techniques well known to one skilled in the art. The memory cell transistors are floating gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
Conventionally, prior to programming the floating gate of a memory cell is biased to a negative voltage relative to the substrate by storing electrons into the floating gate. A floating gate of a memory cell is then programmed by turning the select source and drain transistors off to isolate the series of memory cells, biasing a control gate at the programming voltage, and grounding the body region. The substrate is biased, while the control gate is grounded, thereby driving the electrons from the floating gate back into the substrate.
Each NAND memory cell can be programmed into one of several states which can be designated, for example as follows:
(0,0) denotes an erased state; PA1 (0,1) denotes a partially erased state; PA1 (1,0) denotes a partially programmed state; and PA1 (1,1) denotes a programmed state.
Currently, several reference voltages (Vref1, Vref2 and Vref3) are applied to NAND memory cells for sensing the state of a memory cell. The reference voltage and the state of the memory cell determine a cell current in a sensing circuit. For example a memory cell is conductive when erased, and hence pulls down the sense node. If the memory cell is programmed then it is not conductive and the sense node is pulled up. The state of the memory cell can be determined by analyzing the variation in the current in the sensing circuit caused by applying a reference voltage. "A Non-Volatile semiconductor memory device for storing multivalue data and readout/write-in method" is disclosed in U.S. Pat. No. 5,751,634. (Itoh). Similar to the method described above, in Itoh, reference voltages are applied at individual memory cells during data writing and data readout time, generating memory cell current in response to the reference voltages. The variation in memory cell currents provide the state of the memory cell. The disadvantage of Itoh is that when high reference voltages are applied to a memory cell, the reference voltage may cause disturbance in memory cells adjacent to the memory cell that is sensed at a given time.
Another method to sense the state of a NAND memory cell is by applying an external bias current at 0v and evaluating a cell current generated in response to the external bias current. The disadvantage of such a method is that only two states (0,0) and (1,1) can be sensed.
Therefore, what is desired is a circuit and a method that efficiently senses the levels of a multi state NAND memory cell without causing significant disturbance to memory cells adjacent to the memory cell sensed at any given time.